On Sat, 10 Aug 2002, Jon Masters wrote:
> On Sat, 10 Aug 2002, Robert Davies wrote:
>
> > Hardware trap vectors are common, it's one of the advantages of APICs, you
> > have fewer shared interrupt chains.
>
> We're talking about different things ;-) SPARC defines 5 trap levels with
> separated GPRs - at least the more recent chips do according to the docs.
Which might explain a joke I made to a certain member of this list about a
certain organisation being as useful as a level 4 SPARC trap[0].
Jon.
[0] Level 4 is an error state...
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